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Table 1 from Design of Low Power High Speed Adders in McCMOS Technique ...
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Figure 1 from A 65nm embedded low power SRAM compiler | Semantic Scholar
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Table 1 from A comparative analysis of 128 bytes SRAM architecture ...
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Table 1 from Low-power SRAM circuit design | Semantic Scholar
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Figure 1 from SA Novel Low Power 12T SRAM Cell with Improved SNM ...
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Table 2 from Ultra high density 3D SRAM cell design in Stacked ...
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Table 1 from Reconfigurable tiles of computing-in-memory SRAM ...