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Figure 1 from A bypass-based low latency network-on-chip router ...
Figure 1 from A 100Gbps-ready Low Latency on-Chip Router for FPGA ...
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Figure 1 from A efficacy of different buffer size on latency of network ...
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Figure 2 from Ultra-low latency reconfigurable Photonic Network on Chip ...
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Figure 1 from A practical low-latency router architecture with wing ...
Figure 1 from A Latency-Optimized Network-on-Chip with Rapid Bypass ...
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Figure 1 from An Overview of Low latency for Wireless Communications ...
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Table III from Design of a Low-Latency Router Based on Virtual Output ...
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