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Figure 1 from A log-domain implementation of the Izhikevich neuron ...
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Figure 1 from Low power analog VLSI implementation of cortical neuron ...
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Figure 1 from Evaluations of Electronic Neuron Model for Low Power VLSI ...
Table I from A Low Power Hardware Implementation of Izhikevich Neuron ...
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Figure 5 from A new neuron model suitable for low power VLSI ...
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(PDF) A log-domain implementation of the Izhikevich neuron model
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Figure 5 from A modified Izhikevich model for circuit implementation of ...
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(PDF) A log-domain implementation of the Izhikevich neuron model
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Figure 1 from Analog VLSI Implementation of Neural Network Architecture ...
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(PDF) Implementation of the Izhikevich Neuron Spiking Model - Term ...
Figure 1 from Izhikevich neuron circuit using stochastic logic ...
Some of the neuron dynamics in the Izhikevich model, from [14 ...
(PDF) A Subthreshold aVLSI Implementation of the Izhikevich Simple ...