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Figure 5 from A new architecture for the Viterbi decoder for code rate ...
Figure 1 from A convolutional code decoder design using Viterbi ...
Figure 1 from A low-power Viterbi decoder design for wireless ...
Figure 1 from A reconfigurable viterbi decoder for SDR and mobile ...
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Figure 1 from A generic convolutional code Viterbi decoder generator ...
Figure 1 from Design and Implementation of Analog Viterbi Decoder for ...
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Figure 1 from A Variable-Rate Viterbi Decoder in 130-nm CMOS | Semantic ...
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Figure 1 from Design of Efficient Viterbi Decoder for Multicarrier ...
High Speed Viterbi Decoder Design With A Rate Of 1/2 Convolution Code ...
Figure 1 from Design and Architectural Optimization of Viterbi Decoder ...
Figure 1 from A Viterbi decoder architecture based on parallel ...
Figure 1 from Design and Implementation of A Low Power Modified Viterbi ...
Figure 1 from Low power Viterbi decoder design based on reversible ...
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Figure 1 from A high-throughput reconfigurable Viterbi decoder ...
Figure 1 from Design of Soft Viterbi Algorithm Decoder Enhanced With ...
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Figure 1 from An Efficient Low Power Viterbi Decoder Design using T ...
Figure 1 from Design of Multi-Rate Viterbi Decoder with Variable ...
Figure 1 from 76.5-Gb/s Viterbi Decoder for Convolutional Codes on GPU ...
Figure 1 from An Efficient Design of Dynamic VITERBI Decoder ...
Figure 1 from An Efficient Design of Dynamic VITERBI Decoder ...
Figure 1 from DESIGN OF VITERBI DECODER USING HYBRID REGISTER EXCHANGE ...
Figure 1 from Design of Viterbi decoder with modified traceback and ...
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Figure 1 from A Form of List Viterbi Algorithm for Decoding ...
Figure 1 from Low-power pre-decoding based viterbi decoder for tail ...
Figure 1 from Design of Viterbi decoder with minimum transition hybrid ...
Figure 1 from The Design of Efficient Viterbi Decoder and Realization ...
Table 1 from A trace-back-free Viterbi decoder using a new survival ...