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Figure 2 from A low-power VLSI architecture for the Viterbi decoder ...
Table I from A Modified Viterbi Decoder Architecture for Hardware ...
Figure 2 from A new Viterbi decoder design for code rate k/n | Semantic ...
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Figure 2 from A new VLSI design for Viterbi decoder based on ASIP ...
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Figure 2 from Modified Viterbi decoder for HMM based speech recognition ...
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Table 1 from Modified Viterbi decoder for HMM based speech recognition ...
Viterbi decoder architecture for a convolutional code of rate ½ and ...
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Figure 1 from A low-power systolic array-based adaptive Viterbi decoder ...
Figure 2 from SRAM 설계 ( Low Power Embedded Memory Design for Viterbi ...
Viterbi decoder architecture for a convolutional code of rate ½ and ...